Asynchronous threshold networks

Asynchronous threshold networks

Let G = (V, E) be a graph with an initial sign s(v)e { _+ 1} for every vertex vs V. When a vertex v becomes active, it resets its sign to s'(v) which is the sign of the majority of its neighbors (s'(v) = 1 if there is a tie). G is in a stable state if s(v) = s'(v) for all v e V. We show that for every graph G = (V, E) and every initial signs, there is a sequence v~, v 2 ..... v, of vertices of ...

Computing with Truly Asynchronous Threshold Logic Networks

We present simulation mechanisms by which any network of threshold logic units with either symmetric or asymmetric interunit connections (i.e., a symmetric or asymmetric \Hoppeld net") can be simulated on a network of the same type, but without any a priori constraints on the order of updates of the units. Together with earlier constructions, the results show that the truly asynchronous network...

Technology Mapping for Robust Asynchronous Threshold Networks

As process, temperature and voltage variations become significant in deep submicron design, timing closure becomes a critical challenge in synchronous CAD flows. One attractive alternative is to use robust asynchronous circuits which gracefully accommodate timing discrepancies. However, there is currently little CAD support for such robust methodologies. In this paper, an algorithm for technolo...

Asynchronous Networks

Asynchronous on-chip networks

Various kinds of asynchronous interconnect and synchronisation mechanisms are being proposed for designing low power, low emission and high-speed SOCs. They facilitate modular design and possess greater resilience to fabrication time inter-chip and run-time intra-chip process variability. They can provide a solution for low power consumption in chips and simplify global timing assumptions, e.g....